1. Field of the Invention
The invention relates to a circuit for translating signal levels between on the one hand a first logic family type circuit of the saturated type characterized by having two output signal levels and which is driven, by a first d.c. supply source one of the terminals of which constitutes a common potential reference point, and on the other hand a second logic family type circuit of the non-saturated type characterized by having two output signal levels and which is driven by a second d.c. supply source one of the terminals of which is connected to the common potential reference point and the other terminal of which is connected to a voltage having a polarity opposite to that of the first d.c. supply source. The output signals of the first logic circuit are received at a transit terminal of the translator, and are translated into signals, at an output terminal of the translator, at suitable levels for the input to the second logic circuit.
2. Description of the Related Art
In apparatus for processing digital signals, and especially in the modern computers, it is necessary to translate signals having levels corresponding to those of TTL logic (or an equivalent logic) into signals adapted to logic of the ECL/CML type, and conversely.
TTL type logic is commonly used in logic circuits in which low consumption is required and switching speed is not of major importance. For example, in peripheral elements of a computer. However logic of the ECL/CML type in the current switching mode operates at higher speed due to the absence of saturation and the reduced difference or deviation between logic levels. It is therefore utilized advantageously in the central elements of a computer where digital data must be processed at very high speed.
Consequently, it is desirable to be able to translate the signals between these different types of logic circuit whilst ensuring that the optimum transfer conditions are obtained: in fact predetermined switching levels have to be obtained in the presence of a given noise level over a large temperature range in the presence of supply fluctuations. Otherwise, in addition to the criteria of electrical nature there are technological considerations, as the ease of integration of these translator circuits, the required number of elements and hence their complexity and also their sensitivity to the inevitable fluctuations associated with the methods of manufacture.
A translator circuit of the kind described in the preamble is disclosed in U.S. Pat. No. 3,959,666.
In the known circuit, it is found that the voltage at the switching level does not exhibit the desired variability as a function of temperature, that is to say a variability corresponding to two direct voltage drops of semiconductor junctions, as is the case for a logic of the TTL type. As a result, the noise immunity of such a circuit cannot satisfy the standard requirements over the whole range of usually specified temperatures.
Furthermore, the known circuit makes use of a Schottky diode in parallel with the base-collector junction of a transistor so that saturation of the transistor is avoided. The integration of this type of diode can be effected when the translator circit is constructed according to TTL technology, but can become impossible where contrary, the circuit is constructed according to CML technologies.
Of course, attempts can be made to eliminate the Schottky diode or to replace it by an anti-saturation transistor. In the first alternative, the saturation of the transistor leads to a loss of speed which is not acceptable. In the second alternative, the diode is replaced by a transistor to which supplementary resistors have to be added so that the circuit then requires a comparatively large number of components to obtain the desired switching speed.